Azimuth interpolator

ABSTRACT

An azimuth interpolator is disclosed which receives as an input a sequence of a fixed number of azimuth change pulses for each revolution of a rotating antenna. The time periods between adjacent pairs of the input pulses are assumed to be nearly, but not necessarily, equal. The interpolator includes a first counter which measures the time period between each pair of pulses by accumulating a count which is related to the measured period. At the end of the measured period, the count is transferred to a register which holds the count while the first counter measures a succeeding period. During the latter period, a second counter is clocked at a rate which is greater than the clocking rate of the first counter by a factor X. Each time the count in the second counter equals the count in the register, a pulse is produced which is inserted between the two input pulses which define the period being measured. The interpolator includes an inhibit structure which prevents the Xth pulse from being inserted either immediately before or after the input pulse which defines the end of the period which is being measured.

United States Patent Ballantyne [451 May 2, 1972 [54] AZIMUTHINTERPOLATOR [72] Inventor: Jack R. Ballantyne, Santa Ana, Calif.

[73] Assignee: Hughes Aircraft Company, Culver City,

Calif.

[22] Filed: May 25, 1970 [21] Appl. No.: 40,014

Primary Examiner-Malcolm F. l-lubler AnorneyJames K. Haskell and Walter.1. Adam [5 7] ABSTRACT An azimuth interpolator is disclosed whichreceives as an input a sequence of a fixed number of azimuth changepulses for each revolution of a rotating antenna. The time periodsbetween adjacent pairs of the input pulses are assumed to be nearly, butnot necessarily, equal. The interpolator includes a first counter whichmeasures the time period between each pair of pulses by accumulating acount which is related to the measured period. At the end of themeasured period, the count is transferred to a register which holds thecount while the first counter measures a succeeding period. During thelatter period, a second counter is clocked at a rate which is greaterthan the clocking rate of the first counter by a factor X. Each time thecount in the second counter equals the count in the register, a pulse isproduced which is inserted between the two input pulses which define theperiod being measured. The interpolator includes an inhibit structurewhich prevents h pulse from being inserted either immediately before orafter the input pulse which defines the end of the period which is beingmeasured.

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The invention herein described was made in the course of or under acontract or subcontract thereunder with the Air Force.

BACKGROUND OF THE INVENTION 1. Field of the Invention The presentinvention generally relates to radar circuitry and, more particularly,to an azimuth interpolator for enhancing azimuth output signals inradars of the type which provide a fixed number of azimuth change pulsesper antenna revolution.

2. Description of the Prior Art:

In certain types of radar, such as a fan-beam surveillance radar, afixed number of azimuth change pulses, hereafter designated as A0, areprovided per one full antenna rotation. Clearly, the effective azimuthaccuracy of such a radar is limited by the number of A pulses. Theeffective azimuth accuracy could be greatly increased if the actualnumber of A0 pulses which are provided per antenna revoluation or scanperiod could be increased.

Assuming the number of pulses per revolution or scan period to be 1,024,each pulse represents an azimuth change of 360/ 1,024 degrees. Generallythe A0 pulses following a north-indicating pulse are accumulated in acounter whose output represents azimuth position. Due to the large massof the radar antenna, it does not change rotation rate rapidly.Consequently, the change in period between adjacent A0 pulses is verysmall. However, over a full antenna revolution, due to imperfectmechanical couplings, some change in period is noticable.

It is appreciated that effective azimuth accuracy can be greatlyincreased by increasing the number of A0 pulses per antenna revolution.Since in the prior art the number of pulses is fixed, it is desirable toprovide an arrangement to selectively increase the number of pulses by aselected factor to increase azimuth accuracy. Such an arrangement can bethought of as an azimuth interpolator.

OBJECTS AND SUMMARY OF THE INVENTION It is a primary object of thepresent invention to provide a novel azimuth interpolator for use in aradar system.

Another object of the present invention is to provide a novelarrangement for increasing the number of azimuth change pulses, inresponse to a fixed number of pulses received from a rotating antenna,in order to increase azimuth resolution.

A further object of the invention is to provide a highly reliablearrangement with which the number of azimuth change pulses which areproduced in response to a fixed number of azimuth change pulses providedby a rotating antenna is increasable by a selected factor for increasedazimuth resolution.

These and other objects of the invention are achieved by measuring thetime period between each pair of adjacent A0 pulses, provided from therotating antenna. Then, while a succeeding time period is measured, thepreviously measured period is divided by a selected factor and based onthis factor a selected number of pulses are inserted between thefollowing two adjacent A0 pulses. For example, when the period isdivided by a factor of 2, 4 or 8, and one, three or seven pulses,respectively, are inserted between the following two adjacent pulses.

The novel features of the invention are set forth with particularity inthe appended claims. The invention will be best understood from thefollowing description when read in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simple diagram useful inexplaining the type of input pulses provided in the present invention;

F IG. 2 is a basic block diagram of the invention;

FIG. 3 is a multiline waveform diagram useful in explaining theoperation of the invention shown in FIG. 2; and

FIG. 4 is a block diagram of a pulse inhibiting structure,

which forms part of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The function of the novelazimuth interpolator of the preset invention may best be explained byfirst referring to FIG. 1 wherein numeral 12 designates a rotatingantenna driven by an antenna drive unit 14. As is appreciated by thosefamiliar with the art, such an assembly provides a sequence of azimuthchange or A0 pulses, designated in FIG. 1 by numerals 15-20. The numberof pulses per antenna revolution is fixed and for explanatory purposesis assumed to be 1,024.

Clearly, with a fixed number of pulses, the time period between adjacentA0 pulses is a function of the time required for one complete antennarevolution, sometimes referred to as the scan period. If the time periodbetween adjacent A0 pulses were constant, a relatively simplearrangement could be used to insert a selected number of pulses betweenadjacent A0 pulses. However, this in not the case. Due to mechanicalcoupling inaccuracies, the time period is not a constant. Designatingtwo non-contiguous time periods as P1 and P3, the two are often unequal.Contiguous time periods, such as P1 and P2 can be regarded to be equal,since the radar antenna is a large mass and therefore its rotation ratecannot change rapidly. However, some small difference may exist betweencontiguous time periods.

Briefly, in accordance with the teachings of the present invention, thetime period, such as P between adjacent A0 pulses l5 and 16, ismeasured. Then while period P is measured, previously measured timeperiod P is divided by a selected factor, such as 2, 4 or 8 and one,three, or seven pulses respectively are inserted between the followingtwo adjacent A0 pulses 16 and 17. These functions are performed by thenovel interpolator which is shown in simplified block form in FIG. 2.

Briefly, time period measurement is performed by counter 22, time perioddivision by counter 24, the generation of additional azimuth changepulses by comparator 26 and pulse insertion by an OR gate 27. Basically,counter 22 is clocked by clock pulses which are supplied thereto from aclock 30 through a clock pulse divider 32, shown comprising threeflipflops FFl-FF3. Thus, the clocking rate of the counter 22 isone-eighth the pulse rate from clock 30.

In practice, the number of stages or bits of counter 22 depends on therate at which it is clocked and the maximum spacing or time period P,between adjacent A0 pulses. Assuming a scan period of 16 seconds and1,024 A0 pulses per antenna revolution, the average period is 16/1,O24=l5.6ms. Assuming that the maximum period is 16.384ms and that thecounter 22 is clocked by clock pulses of a clock period of 64,125, it isapparent that during the maximum period, 256 or 2 counts can beaccumulated in counter 22 without exceeding its maximum count. Thus, itcan be stated that the counter 22 is chosen to be of a length so thatfor a given clock rate a maximum count can be accumulated therein duringthe period which is measured without exceeding the counters maximumCOUI'II.

It is apparent that if the counter 22 is assumed to be clocked at a rateof once per 64p.s, the clock period from the clock 30 is 64/8=8;Lp.s,and 32p.s, respectively.

As shown, when a A0 pulse is received from the antenna it resets thecounter 22 and the FPS of the clock dividing network 32. It alsoprovides a load signal to a register 35 which is loaded with theaccumulated count in the counter 22 before the latter is reset. Toinhibit the counter 22 from being reset before the register is loadedwith its count, the resetting signal to the counter may be delayed by aclock period in manners well known in the art. Each A0 pulse from theantenna further resets counter 24 through an OR gate 33, and is suppliedas a real A0 pulse, hereafter designated as A0,; to output Or gate 27.

The content of register 35 is supplied to comparator 26, which comparesthe registers content or count with the count in the counter 24. Thelatter is clocked at a rate which is greater than the clocking rate ofcounter 22 by a selected factor such as 2, 4, etc., depending on thenumber of pulses which are to be inserted between adjacent A pulses fromthe antenna. For example, to insert a single pulse between adjacent A0pulses, i.e., to increase the number of azimuth change pulses by afactor of 2 represented by 2X, an AND gate 36 is enabled. The gate issupplied with the output of FFZ which is at twice the clocking rate ofcounter 22. Gate 36 enables OR gate 37 whose output has a clockingperiod which is half the clocking period of counter 22. Thus, counter 24is clocked at twice the clocking rate of counter 22.

When the accumulated count in counter 24 equals the count in register35, comparator 26 provides an output pulse. This pulse can be thought ofas a synthetic A0 pulse, and is designated A0 It resets counter 24through gate 33 and is also supplied to output gate 27. The output ofthe latter is the composite of the real A0 pulses from the antenna,designated A0,; and the synthetic pulses A0 from the comparator.

The insertion of three pulses A0 between a pair of real A0 pulses isaccomplished by activating AND gate 38 which is supplied with clockingpulses from FF 1 at four times the clocking rate of counter 22. This isdone by setting the terminal designated X4 to a true level.Consequently, counter 24 is clocked at four times the clocking rate ofcounter 22. The insertion of seven synthetic pulses between a pair ofreal A0 pulses is achieved by enabling gate 39 with the clock pulsesfrom clock 30 which are provided at eight times the clocking rate ofcounter 22 so counter 24 is clocked at eight times the clocking rate ofcounter 22. This is achieved by setting the terminal X8 of gate 39 to atrue level.

The foregoing description of the operation of the interpolator may bestbe summarized in connection with a specific example which will bedescribed in conjunction with FIG. 3. For this example, it is assumedthat the maximum spacing between real A0 pulses is 16.384ms, counter 22is eight bits long and its clock period is 64us. Let it be assumed thatthe period P1 between pulses and 16 is such that when pulse 16 arrivesat I, the count in counter 22 is 250. This count is transferred toregister 35 at 1 and then counter 22 is reset to accumulate a countwhich represents the period P2 between pulse 16 and the succeeding pulse17. Also gate 27 is enabled at t, to provide an output pulsecorresponding to A0 pulse 16. The pulse which is supplied to gate 27 isdesignated by 16a and the corresponding output pulse real A0 pulse isdesignated 16b.

Let it be assumed that it is desired to insert three pulses betweenpulse 16 and its succeeding pulse 17. Under these conditions gate 38 isenabled to clock counter 24 at four times the clocking rate of counter22. While counter 22 accumulates the count which is to represent ameasure of period P2, the count in register 35 is 250 which representsthe previously measured period Pl. Each time the count in counter 24reaches 250, comparator 26 provides a synthetic pulse A0 which issupplied to gate 27. The three pulses which are supplied to gate 27between pulses 16 and 17 are designated by numerals 41, 42 and 43 andthe corresponding output pulses of gate 27 are designated by numerals41a, 42a and 43a, respectively.

Clearly, if period P2 were exactly equal to period P1 which isrepresented by the number 250 in register 35, pulse 17 will be receivedby the interpolator and be supplied to gate 27 as pulse 17a at the sameinstant that a fourth pulse 44 will be supplied thereto from comparator26. The two coincident in-time pulses will result in a single gate 27output, designated as pulse 17b. If, however, a slight differencebetween the two adjacent time periods P1 and P2 is present, the twopulses 17a and 44 will not be coincident in time and consequently willresult in two adjacent output pulses of gate 27. For example, if P2 Plpulse 44 will occur prior to pulse 17a as represented in FIG. 3 by pulse44 in dashed lines. Consequently, output pulse 17b will be preceded byan adjacent pulse 44a. On the other hand, if P2 P1 pulse 44 would occurafter pulse 170 and therefore pulse 44a would follow pulse 17b.

Such an operation will result in an unequal spacing between the outputpulses of gate 27. To prevent this condition from occurring, theinterpolator includes a gating structure shown in FIG. 4 which isdesigned to inhibit a synthesized pulse A0 from activating gate 27either immediately before or after a real pulse A0 from the antenna, dueto slight differences between the lengths of adjacent time periods.Basically, the gating structure includes a multibit counter 51. For thearrangement in which either one, three or seven synthetic pulses A0; areto be inserted between a pair of adjacent A0 pulses. The counterincludes three stages or bits 81-83. The counter is clocked by eachsynthetic pulse A0 from the comparator 26 and is reset by each A0 pulsefrom the antenna. For the particular example, 5 AND gates 52-56 and ORgate 57 and an inverter 58 are associated with the counter. The inverteroutput is true depending on the count in counter 51 and the clockingrate of counter 24 which controls the number of synthetic pulses to beinserted. The output of the inverter 58 and the output of comparator 26are supplied to AND gate 60 whose output is ORed with the real A0 pulsesin OR gate 27.

Briefly, when the counter 24 is clocked at four times (X4) the clockingrate of counter 22, the outputs of gates 54 and 56 are always false.Consequently, gate 57 can only be turned on by gate 55. When the countin the counter 51 is less than three, gate 52 is turned off and so isgate 55. Consequently, the output of gate 57 is false and the output ofinverter 58 is true. This enables each of the three pulses A0 from thecom parator, such as pulses 41-43 to enable gate 60 which in turnenables output gate 27 to provide pulses 41a, 42a and 43a, respectively.However, after three pulses are provided by the comparator, gate 52 isturned on turning on gates and 57. Consequently, the inverter output isfalse, thereby inhibiting a fourth pulse, such as pulse 44 whichproceeds the next A0 pulse from activating gates and 27.

It should be apparent that when the X2 clocking rate is employed, aftera single pulse A0 is inserted, gate 54 is turned on, in turn activatinggate 57. Consequently, the inverters false output inhibits a succeedingpulse A0 from activating gates 60 and 27. Similarly, when the X8clocking rate is employed, the first seven pulses A0 pass through gates60 and 27. The seventh pulse sets counter 51 to an all one state therebyenabling gate 53, which in turn enables gates 56 and 57. Consequently,the inverters false output inhibits the eight pulse A0 from activatinggate 60 and more particularly, output gate 27.

From the foregoing it is thus seen that in accordance with the presentinvention, one or more synthetic azimuth change pulses A0 can beinserted between each pair of real azimuth change pluses A0 from therotating antenna. The number of inserted synthetic pulses can be definedas X-l, where X represents the number into which a previously measuredtime period, such as P1 between two successive azimuth change pulse A0,such as 15 and 16 is divided, while a succeeding time period such as P2between another pair of pulses, such as 16 and 17, is measured. The timeperiod division is achieved by clocking a counter, such as counter 24,as X times the rate at which a clock such as clock 22 which is used tomeasure the time period to be divided is clocked. The factor X may beequal to 2" where n is an integer. Consequently, 2"l synthetic pulsesare inserted between each pair of real A0 pulses. For example, when n iseither 1, 2 or 3, i.e., the time period is divided by 2=2, 2 =4 or 2 =8,the number of inserted pulses is 2--l=l, 2 l=3 or 2*1= 7.

It should be appreciated that although the invention has been describedin connection with simple AND and OR gates other types of gates such asNAND and NOR gates may be employed to perform the desired logicfunctions. It should further be appreciated that the invention may beemployed to insert equally spaced pulses between each pair of inputpulses in a sequence of input pulses, where the periods between adjacentpairs of input pulses are nearly, but not necessarily, equal.

It should be stressed that for the present invention, it is assumed thattwo adjacent periods such as P1 and P2 are nearly but not necessarilyequal. if adjacent periods are equal, i.e., if the period between anytwo adjacent input pulses is the same, the need for the invention isgreatly reduced. 0n the Other hand, if the difference between adjacentperiods is great, the inserted pulses cannot be uniformly spaced betweenthe two pulses. The tolerable difference clearly depends on the desiredaccuracy of the spacing of the inserted pulses.

Although particular embodiments of the invention have been described andillustrated herein, it is recognized that modifications and variationsmay readily occur to those skilled in the art and, consequently, it isintended that the claims be interpreted to cover such modifications andequivalents.

What is claimed is:

1. In a radar system of the type including a rotatable antenna and meanswhich provide a sequence of antenna azimuth change indicating pulses,said sequence including a fixed number of azimuth change indicatingpulses for each antenna revolution, an arrangement comprising:

first means responsive to said pulse sequence for measuring the timebetween a pair of successive pulses in said sequence;

second means for containing said measured time period while said firstmeans measure a succeeding time period between a succeeding pair ofpulses; third means for dividing the measured time period contained insaid second means into X equal time periods, while said first meansmeasure said succeeding time period, and for providing a pulse at theend of each of said X time periods; and

fourth means for combining said azimuth change indicating pulses withthe pulses from said third means to provide a sequence of pulsescomprising said azimuth change indicating pulses with X-l pulses betweeneach pair of azimuth change indicating pulses.

2. The arrangement as recited in claim 1 wherein X=2" where n is aninteger.

3. The arrangement as recited in claim 1 wherein successive time periodsbetween successive pairs of azimuth change indicating pulses in saidsequence are unequal, and said fourth means include means for inhibitingthe (X1)" pulse provided by said third means when said measured timeperiod is divided into X equal time periods from being included in thesequence provided by said fourth means.

4. The arrangement as recited in claim 1 wherein said first meanscomprises a first counter, and said arrangement includes means forclocking said counter at a first clocking rate to accumulate a counttherein during the time period to be measured, with the count beingdirectly related to said measured time period, said second meanscomprising a register for receiving at the end of the measured timeperiod the count accumulated in said first counter, and for containingsaid count during a subsequent time period, measured by said firstcounter, said third means comprising a second counter clockable at asecond clockable rate which is greater than said first rate by a factorX, and comparing means for comparing the count in said register with thecount in said second counter and for providing an output pulse wheneverthe two counts are equal, and means for resetting said second counterwith the output pulse of said comparator.

5. The arrangement as recited in claim 4 wherein X=-2" wherein n is aninteger.

6. The arrangement as recited in claim 5 wherein successive time periodsbetween successive pairs of azimuth change indicating pulses in saidsequence are unequal, and said fourth means include means for inhibitingthe (Xl)"' pulse, provided by said third means when said measured timeperiod is divided into X equal time periods, from being included in thepulse sequence provided by said fourth means.

7. An arrangement responsive to a sequence of separate input pulsesincluding first, second and third pulses for providing an outputsequence of output pulses, said out ut sequence containing an outputpulse corresponding to eacii input pulse and additional pulses insertedbetween each pair of output pulses which correspond to a pair of inputpulses, the arrangement comprising:

a first counter clockable at a first rate for accumulating a count whichcorresponds to the time period between each pair of input pulses;

a register responsive to said second input pulse for receiving the countaccumulated in said first counter during the time period between saidfirst and second input pulses and for holding said count therein duringthe period between said second and third input pulses;

a second counter clockable during the time period between said secondand third input pulses at a second rate which is greater than said firstrate by a factor X, X being an integer greater than 1;

a comparator responsive to the contents of said register and said secondcounter for providing a pulse each time the counts in the second counterand the register are equal, and

output means for providing an output sequence of output pulses whichinclude an output pulse for each input pulse and a pulse correspondingto each pulse provided by said comparator, said output means includingmeans for providing a single output pulse when an input pulse and apulse from said comparator are supplied thereto in time coincident.

8. The arrangement as recited in claim 7 wherein said output meansinclude means for including in said output sequence the first X-l pulsesprovided by said comparator during a measured time period betweensuccessive input pulses and for inhibiting the X" pulse from beingincluded in said output sequence.

9. The arrangement as recited in claim 7 wherein the time periodsbetween adjacent pairs of input pulses are not equal and said outputmeans include means for including in said output sequence the first X-lpulses provided by said comparator during a measured time period betweensuccessive input pul ses and for inhibiting the X'" pulse from beingincluded in said output sequence.

10. The arrangement as recited in claim 9 wherein X=2" wherein n is aninteger.

1. In a radar system of the type including a rotatable antenna and meanswhich provide a sequence of antenna azimuth change indicating pulses,said sequence including a fixed number of azimuth change indicatingpulses for each antenna revolution, an arrangement comprising: firstmeans responsive to said pulse sequence for measuring the time between apair of successive pulses in said sequence; second means for containingsaid measured time period while said first means measure a succeedingtime period between a succeeding pair of pulses; third means fordividing the measured time period contained in said second means into Xequal time periods, while said first means measure said succeeding timeperiod, and for providing a pulse at the end of each of said X timeperiods; and fourth means for combining said azimuth change indicatingpulses with the pulses from said third means to provide a sequence ofpulses comprising said azimuth change indicating pulses with X1 pulsesbetween each pair of azimuth change indicating pulses.
 2. Thearrangement as recited in claim 1 wherein X 2n where n is an integer. 3.The arrangement as recited in claim 1 wherein successive time periodsbetween successive pairs of azimuth change indicating pulses in saidsequence are unequal, and said fourth means include means for inhibitingthe (X-1)th pulse provided by said third means when said measured timeperiod is divided into X equal time periods from being included in thesequence provided by said fourth means.
 4. The arrangement as recited inclaim 1 wherein said first means comprises a first counter, and saidarrangement includes means for clocking said counter at a first clockingrate to accumulate a count therein during the time period to bemeasured, with the count being directly related to said measured timeperiod, said second means comprising a register for receiving at the endof the measured time period the count accumulated in said first counter,and for containing said count during a subsequent time period, measuredby said first counter, said third means comprising a second counterclockable at a second clockable rate which is greater than said firstrate by a factor X, and comparing means for comparing the count in saidregister with the count in said second counter and for providing anoutput pulse whenever the two counts are equal, and means for resettingsaid second counter with the output pulse of said comparator.
 5. Thearrangement as recited in claim 4 wherein X 2n wherein n is an integer.6. The arrangement as recited in claim 5 wherein successive time periodsbetween successive pairs of azimuth change indicating pulses in saidsequence are unequal, and said fourth means include means for inhibitingthe (X-1)th pulse, provided by said third means when said measured timeperiod is divided into X equal time periods, from being included in thepulse sequence provided by said fourth means.
 7. An arrangementresponsive to a sequence of separate input pulses including first,second and third pulses for providing an output sequence of outputpulses, said output sequence containing an output pulse corresponding toeach input pulse and additional pulses inserted between each pair ofoutput pulses which correspond to a pair of input pulses, thearrangement comprising: a first counter clockable at a first rate foraccumulating a count which corresponds to the time period between eachpair of input pulses; a register responsive to said second input pulsefor receiving the count accumulated in said first counter during thetime period between said first and second input pulses and for holdingsaid count therein during the period between said second and third inputpulses; a second counter clockable during the time period between saidseconD and third input pulses at a second rate which is greater thansaid first rate by a factor X, X being an integer greater than 1; acomparator responsive to the contents of said register and said secondcounter for providing a pulse each time the counts in the second counterand the register are equal, and output means for providing an outputsequence of output pulses which include an output pulse for each inputpulse and a pulse corresponding to each pulse provided by saidcomparator, said output means including means for providing a singleoutput pulse when an input pulse and a pulse from said comparator aresupplied thereto in time coincident.
 8. The arrangement as recited inclaim 7 wherein said output means include means for including in saidoutput sequence the first X-1 pulses provided by said comparator duringa measured time period between successive input pulses and forinhibiting the Xth pulse from being included in said output sequence. 9.The arrangement as recited in claim 7 wherein the time periods betweenadjacent pairs of input pulses are not equal and said output meansinclude means for including in said output sequence the first X-1 pulsesprovided by said comparator during a measured time period betweensuccessive input pulses and for inhibiting the Xth pulse from beingincluded in said output sequence.
 10. The arrangement as recited inclaim 9 wherein X 2n wherein n is an integer.